A week-long competition where teams build AI-assisted verification environments for real-complexity RTL designs derived from the OpenTitan ecosystem. Participants develop testbenches, drive coverage ...
As the RISC-V ecosystem grows, startups struggle to verify complex chips before tape-out. Chennai-based startup addresses this with a unified, Python-friendly, AI-assisted pre-silicon platform that ...
Its use results in faster development, cleaner testbenches, and a modern software-oriented approach to validating FPGA and ASIC designs without replacing your existing simulator. Verification has ...
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