IEEE

FPGA-Based Low-Power Signed Approximate Multipliers for Diverse Error-Resilient Applications

Abstract: The Booth algorithm is widely used for efficient signed multiplication due to its ability to reduce partial products. A higher radix Booth multiplier generates fewer partial products, while ...
GitHub

Computer Organization and Architecture and Processor Architecture Lab

Computer Organization and Architecture (CSC403) and Processor Architecture Lab (CSL403) are core subjects in the Second Year (Semester IV) of the Computer Engineering curriculum at the University of ...
Europe PMC

Extending the IEEE 802.15.4 security suite with a compact implementation of the NIST P-192/B-163 elliptic curves.

Typically, commercial sensor nodes are equipped with MCUsclocked at a low-frequency (i.e., within the 4-12 MHz range). Consequently, executing cryptographic algorithms in those MCUs generally requires ...
IEEE

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree

Abstract: The modified-Booth algorithm is extensively used for high-speed multiplier circuits. Once, when array multipliers were used, the reduced number of generated partial products significantly ...