Semiconductor Engineering

Reducing The Cost of Cache Coherence By Integrating HW Coherence Protocol Directly With The Programming Language

A new technical paper titled “WARDen: Specializing Cache Coherence for High-Level Parallel Languages” was published by researchers at Northwestern University and Carnegie Mellon University.
Electronic Design

Formal Techniques for Protocol Verification: A Case Study On Verifying the ARM ACE Protocol

More processors on SoCs means more sophisticated cache control. This article describes formal techniques for verifying cache coherency for the ARM AMBA AXI Coherency Extensions (ACE) protocol. Fig 1.
Semiconductor Engineering

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)

“We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to ...
The Next Platform

Eating The Interconnect Alphabet Soup With Intel’s CXL

The dividing lines between system buses, system intraconnects, and system interconnects are getting more blurry all the time. And that is, oddly enough, going to turn out to be a good thing in the ...
EDN

How to use DSP caches, part 2

If multiple devices, such as the CPU and peripherals, access the same cacheable memory region, cache and memory can become incoherent. This is illustrated in Figure 7. Suppose the CPU accesses a ...